In addition, future requirements will need significantly higher performance. As noted above, if the accuracy needs to be increased by 5 percent, then the performance of the DNN must increase by a factor of 10.
The number of sensors and the input layer are also increased. Today's 1 megapixel (MP) sensors will be replaced by multiple MP sensors (8 x 2MP or 4 x 4MP). In other words, the performance should be increased by a factor of multiples of 10 .
Today it is foreseeable that a performance of 4 TOPS (Tera Operations per Second) will be required in 2019 (SoP: Start of Production). By 2022 40 TOPS or even more may be required, in other words: an increase of a factor of multiples of 10 must be achieved.
Staying with traditional CPU/GPU architectures, the best factor to be achieved is x2 within 2 years at the same power consumption switching to the next technology process. The missing factor of 5 (or more) would have to be achieved by higher power consumption, easily bringing power consumption into the 50W range and more. A new paradigm in the computing architecture is required to keep embedded power in a controllable area by providing more dedicated hardware IP. This would not be as flexible as a CPU/GPU but allows much higher computing efficiency.
High performance/low power consumption - both are important
Accordingly, Renesas is pursuing a multi-faceted strategy for the R-Car hardware acceleration.
Renesas is initially focusing on the architecture level design to optimise the external memory bandwidth of the memory, as it has shown like in the R-Car V3M solution. This enables seamless heterogeneous IP integration while meeting the safety requirements of ISO 26262.
The next element of the strategy is to keep improving the existing IP set, for example with the use of more cores, higher frequency and more specialised computing elements.