One key challenge presented by the DAPD is that of being able to interface with a range of different sensor modalities, all of which come with differing interface standards. A typical solution will interface with a range of sensor modalities which use high speed interfaces such as MIPI, JESD204B, LVDS and GigE for high bandwidth interfaces such as cameras, RADAR and LIDAR. The DAPD will also be required to interface with slower interfaces such as CAN, SPI, I2C and UARTs. The processing system (PS) and programmable logic (PL) of the Zynq UltraScale+ MPSoC provide support for a range of industry-standard interfaces including SPI, I2C, UART and GigE, while the flexibility of the PL IO enables direct interfacing with MIPI, LVDS and Giga Bit Serial Links allowing higher levels of the protocol to be implemented within the PL, often using IP cores. Implementation of the protocol within the PL also enables standards revisions to be easily incorporated along with providing flexibility as to the number of specific sensor interfaces supported within a solution. The PL also provides the ability to implement any interface with the provision of the correct PHY in the hardware design providing a true any-to-any interfacing capability.
The programmable logic provided by the Xilinx automotive grade Zynq UltraScale+ MPSoC also enables acceleration of neural networks. The parallel nature of the programmable logic allows the implementation of neural networks which are more responsive and deterministic than a traditional CPU/GPU based approach, as the traditional external memory bottlenecks between stages are removed. These neural networks can be implemented with high level languages like C, C++ and OpenCL using the system-optimising compiler SDSoC which enables functionality to be moved seamlessly from the processor system to the programmable logic.