Revolutionary acceleration can be achieved by integrating dedicated hardware IPs based on the state of the art algorithms to achieve the best performance/power efficiency.
As a result, Renesas continues to rely on ARM cores for standard computing tasks and on the IMP-X5, a heterogeneous computing subsystem for specialised processing. This is composed of a hard-wired part (for the computer-intensive portion and established parts of the DNN algorithms) and on programmable architecture for future-proof, flexible and programmable use with the CV engine.
– a must-have for efficient performance
The IMP-X5 uses approaches from the IMP core, which the company launched in 2009 and has been integrated in Renesas products for more than 10 years. One of the first applications for this hardware accelerator was a neural network. Already in 2009, Renesas was able to show that the core performs much better than a standard CPU: to process NN algorithms the CPU needed 204 ms, while the IMP core took only 8.9 ms.
The hard-wired IMP core (8-/16-bit integer) is a computing unit with pixel and line interconnects. Thanks to the memory-centric architecture - the data is almost streamed by feeding the pipeline with one pixel per cycle and one pixel per cycle is stored - the memory accesses are minimised.
In the near future, the IMP core and the CV engine will be expanded by additional IPs, which enable, for example, a high-performance, energy-saving implementation of CNNs.